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Cadence Design Systems has announced the delivery of the Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity by up to 10X versus a manual approach while also realising up to a 20 per cent better power, performance and area (PPA).
With the addition of Cerebrus to the broader digital product portfolio, Cadence offers the industry’s most advanced ML-enabled digital full flow, from synthesis through implementation and signoff. The new tool is cloud enabled on Amazon Web Services (AWS) and other leading cloud platforms and utilises highly scalable compute resources to rapidly meet design requirements across a wide range of markets including consumer, hyperscale computing, 5G communications, automotive and mobile.
“Previously, design teams did not have an automated way to reuse historical design knowledge, leading to excess time spent on manual re-learning with each new project and lost margins. The delivery of Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organizations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus lets designers achieve PPA goals much more efficiently,” said Dr. Chin-Chi Teng, Senior Vice President and General Manager, Digital and Signoff Group, Cadence.
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